This invention relates to vector processing apparatus and, in particular, to vector processing apparatus for performing iterative operation at a high speed.
Iterative operations requires a previous result of operation for subsequent operation. That is, the an iterative operation is generally given by a general an equation: EQU x(i)=f(x(i-1)), (1)
where i represents a positive integer and f(x(i-1)) denotes a function of a variable x(i-1).
Attention will be directed to an example of the iterative operation which is given by a particular equation: EQU x(i)=b(i)+a(i)*x(i-), (2)
where a(i) represents each of primary vector operand elements of first vector operand data and b(i) represents each of secondary vector operand elements of second vector operand data.
In order to perform the iterative operation given by the particular equation (2), a conventional vector processing apparatus comprises a first operand vector register for storing the first vector operand data and a second operand vector register for memorizing the second vector operand data.
A first readout unit reads one of the primary vector operand elements of the first vector operand data out of the first operand vector register as a primary read element to supply to a multiplying unit the primary read element as a primary input element of first input data. In the manner which will become clear as the description proceeds, the multiplying unit is supplied with a secondary input element of second input data. The multiplying unit carries out a multiplication operation on the primary input element of first input data and the secondary input element of second input data to produce a primary result element of first result data.
The primary result element of the first result data is delivered to an adding unit as a ternary input element of third input data. A second readout unit reads one of the secondary operand elements of the second vector operand data out of the second operand vector register as a secondary read element to supply the secondary read element to the adding unit as a quaternary input element of fourth input data. The adding unit carries out an addition operation on the ternary input element of third input data and the quaternary input element of fourth input data to produce a secondary result element of second result data.
A writing unit writes the secondary result element of the second result data in a result vector register as a vector result element of vector result data. The secondary result element of the second result data is delivered to the multiplying unit as a following secondary input element of the second input data.
In general, each of the multiplying unit and the adding unit is operable under pipeline control. It is assumed that the multiplying unit and the adding unit are operable under six-stage and four-stage pipeline control, respectively. In this event, it takes twelve machine cycles to provide the vector result element of the vector result data in the manner which will later be described. Therefore, the conventional vector processing apparatus can not give full play to its ability for performing the iterative operation.
In order to suppress deterioration in performance of a process as regards the iterative operation, a time-sharing method is disclosed in the specification of U.S. Pat. No. 4,757,444 issued to Tomoo Aoyama et al and assigned to Hitachi, Ltd. According to Aoyama et al, the particular equation (2) is modified into a modified equation as follows: EQU x(i+1)=(b(i)*a(i+1)+b(i+1))+(a(i)*a(i+1))*x(i-1).
The iterative operation given by the modified equation is time-sharingly performed by using the multiplying unit and the adding unit. However, vector processing apparatus carrying out the time-sharing method must carry out complex control in the manner which will later be described.